1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a test mode.
2. Description of the Background Art
In general, a semiconductor memory device is provided with an internal boost power-supply (hereinafter referred to as VPP) generating circuit as a power-supply for charging word lines in a memory cell array, and is further provided with a reference potential generating circuit supplying a reference potential to the VPP generating circuit.
Moreover, a semiconductor memory device having a test mode is provided with a test mode reference potential generating circuit, i.e. a reference potential generating circuit for the test mode, in addition to the reference potential generating circuit used in a normal operation.
FIG. 14 is a circuit diagram of a test mode reference potential generating circuit in a semiconductor memory device having a test mode.
Referring to FIG. 14, the test mode reference potential generating circuit includes resistance elements 1, 2 and an N-channel MOS transistor 3. Resistance element 1 is connected between a power-supply node VCC and an output node B1. Resistance element 2 has one end connected to output node B1 and the other end connected to the drain of N-channel MOS transistor 3. The source of N-channel MOS transistor 3 is connected to a ground node 4, and a test mode signal TM activated in the test mode is input into the gate of N-channel MOS transistor 3.
During the test mode, the test mode signal TM input into the gate of N-channel MOS transistor 3 is activated (to be at a logic high or xe2x80x9cHxe2x80x9d level), and thus N-channel MOS transistor 3 is turned on. As a result, the test mode reference potential generating circuit divides an external power-supply potential VCC by resistance elements 1 and 2, and outputs the divided potential from output node B1 as a reference potential Vref to be supplied to the VPP generating circuit.
The test conducted in the semiconductor memory device including the test mode reference potential generating circuit having such a circuit configuration is often used in a burn-in. In the burn-in, it is undesirable for the potential output from the VPP generating circuit to vary during the test mode. This is because, the acceleration factor of a gate oxide film is usually determined on the basis of a potential value output from the VPP generating circuit, i.e. the highest potential, so that the raise of the potential output from the VPP generating circuit as a result of the raised external power-supply potential VCC by the operation of the device during the test would apply an excessive stress to the device, which may result in destruction of the device. Moreover, if the operation of the device consumes excessive current, external power-supply potential VCC is lowered, preventing application of a desired stress to the device.
However, in the conventional semiconductor device, the potential divided from external power-supply potential VCC was always supplied to the VPP generating circuit as a reference potential Vreft during the test mode, as described above, so that reference potential Vreft was directly affected by variations of external power-supply potential VCC, resulting in variations of the value of Vreft.
It is an object of the present invention to provide a semiconductor memory device including a reference potential generating circuit capable of generating a stable reference potential during a test mode.
According to the present invention, a semiconductor memory device having a test mode includes a memory cell array; an internal potential generating circuit generating an internal potential; a reference potential generating circuit generating a reference potential and supplying the reference potential to the internal potential generating circuit; a control circuit controlling the memory cell array in response to a plurality of control signals and address signals input from an external source. The control circuit outputs a test mode signal indicating the test mode in response to the plurality of control signals and address signals, and further outputs a sample signal in response to the test mode signal; and the reference potential generating circuit latches the reference potential in response to the sample signal and supplies the latched reference potential to the internal potential generating circuit.
Thus, the reference potential latched during the test mode is supplied to the internal potential generating circuit, so that the internal potential is stabilized during the test mode.
Preferably, the reference potential generating circuit includes an output stage outputting the reference potential in response to the test mode signal, a latch stage latching the reference potential output from the output stage, and a switch stage connecting the output stage to the latch stage in response to the sample signal.
More preferably, the latch stage includes a capacitor, and the switch stage includes a transfer gate which is turned on in response to the sample signal.
This allows external power-supply potential VCC to be cut off from the internal potential generating circuit when the test is executed.
Preferably, the latch stage includes a register; and the reference potential generating circuit further includes an analog-to-digital converting circuit converting the reference potential output from the output stage from an analog value into a digital value to be supplied to the register via the switch stage and a digital-to-analog converting circuit converting the reference potential output from the register from a digital value into an analog value.
This eliminates the needs for the latch stage to frequently latch the reference potential from the output stage during the test mode.
More preferably, the control circuit includes a command decoder receiving the control signal and outputting a command, an address decoder receiving the address signal and outputting a signal, a test signal generating circuit generating the test signal by a combination of the command output from the command decoder and the signal output from the address decoder, and a sample signal generating circuit outputting a sample signal in response to the test signal.
This enables generation of a test signal and a sample signal by a combination of a control signal and an address signal.
More preferably, the sample signal generating circuit generates the sample signal by a combination of the test signal, a mode register setting command output from the command decoder and the signal output from the address decoder.
More preferably, the sample signal generating circuit generates the sample signal by the combination of the test signal, the control signal and the signal output from the address decoder.
According to the present invention, a semiconductor memory device can be provided, which is capable of supplying a stable reference potential during the test mode without any adverse effect from possible variations of the external power-supply potential due to the device operation or the like.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.